• DocumentCode
    2489027
  • Title

    Parallel delta-sigma A/D conversion

  • Author

    King, Eric ; Aram, Farbod ; Fiez, Terri ; Galton, Ian

  • Author_Institution
    Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
  • fYear
    1994
  • fDate
    1-4 May 1994
  • Firstpage
    503
  • Lastpage
    506
  • Abstract
    This paper presents an architecture wherein multiple delta-sigma modulators are combined so that neither time oversampling nor time interleaving are necessary. For a system containing M Pth-order delta-sigma modulators, approximately P bits of accuracy are gained for every doubling of M. Thus, the resolution gained by combining M delta-sigma modulators is approximately the same as that with the same modulator with an oversampling rate of M. Measured results from a 16-channel parallel delta-sigma A/D converter composed of second-order delta-sigma modulators verify the theory and demonstrate that this architecture retains much of the robustness of the individual delta-sigma modulators to non-ideal circuit behavior
  • Keywords
    CMOS integrated circuits; parallel architectures; sigma-delta modulation; 16-channel configuration; CMOS IC; delta-sigma A/D conversion; multiple delta-sigma modulators; parallel ADC; Circuits; Computer architecture; Computer science; Delta modulation; Digital modulation; Filters; Gain measurement; Interleaved codes; Quantization; Robustness;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    0-7803-1886-2
  • Type

    conf

  • DOI
    10.1109/CICC.1994.379673
  • Filename
    379673