DocumentCode
2489046
Title
A 10-bit, 20-MS/s, 35-mW pipeline A/D converter
Author
Cho, Thomas B. ; Gray, Paul R.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear
1994
fDate
1-4 May 1994
Firstpage
499
Lastpage
502
Abstract
This paper describes a 10-bit 20-MS/s pipeline A/D converter implemented in 1.2-μm CMOS technology which achieves a power dissipation of 35 mW at full speed operation. Circuit techniques used to achieve this level of power dissipation include operation on a 3.3 V power supply, optimum scaling of capacitor values through the pipeline, and digital correction to allow the use of dynamic comparators. Measured performance includes 0.6 LSB of INL, 59.1 dB of SNDR for 100 kHz input at 20 MS/s. At Nyquist sampling (10 MHz input), SNDR is 55.0 dB
Keywords
CMOS integrated circuits; analogue-digital conversion; pipeline processing; 1.2 micron; 10 bit; 3.3 V; 35 mW; CMOS technology; Nyquist sampling; digital correction; dynamic comparators; monolithic ADC; pipeline A/D converter; power dissipation; CMOS technology; Capacitors; Circuits; Operational amplifiers; Pipelines; Power dissipation; Quantization; Sampling methods; Signal resolution; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994
Conference_Location
San Diego, CA
Print_ISBN
0-7803-1886-2
Type
conf
DOI
10.1109/CICC.1994.379674
Filename
379674
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