High performance 3.3 and 5 volt 0.5-μm CMOS technologies for ASICs

Author

Kizilyalli, I.C. ; Thoma, M.J. ; Lytle, S.A. ; Martin, E.P. ; Vitkavage, S.C. ; Singh, R. ; Bechtold, P.F. ; Kearney, J.W. ; Rambaud, M. ; Oates, A. ; Ryan, V. ; Layman, P.A. ; Twiford, M. ; Cochran, W.T.

Author_Institution

AT&T Bell Labs., Allentown, PA, USA

fYear

1994

fDate

1-4 May 1994

Firstpage

11

Lastpage

14

Abstract

Two manufacturable high performance 0.5 pm CMOS technologies, one optimized for 5 V operation and the second optimized for 3.3 V operation, are presented. An improvement of 2 in circuit performance, 3.4 in packing density, 1.5 and 3.2 (for 5 and 3.3 V) in power consumption at constant speed, and 1.45 (for 3.3 V) in power consumption at maximum speed is achieved over AT&T´s previous generation 0.9 μm CMOS technology by device scaling, and aggressive interconnect and isolation design rules

Keywords

CMOS integrated circuits; application specific integrated circuits; integrated circuit design; integrated circuit reliability; integrated circuit technology; 0.5 micron; 3.3 V; 5 V; ASICs; CMOS technologies; device scaling; interconnect design rules; isolation design rules; manufacturable high performance technologies; packing density; power consumption; Application specific integrated circuits; CMOS technology; Dielectrics; Etching; Implants; MOS devices; MOSFETs; Resists; Threshold voltage; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1994., Proceedings of the IEEE 1994

Conference_Location

San Diego, CA

Print_ISBN

0-7803-1886-2

Type

conf

DOI

10.1109/CICC.1994.379777

Filename

379777