Pipelined Hardware Architecture for High-Speed Optical Flow Estimation Using FPGA

Optical flow is a motion field estimation method that has a wide range of applications. In this paper, we present a fully pipelined hardware architecture for high-speed optical flow estimation based on a full-search block matching algorithm. A census transform is applied to the corresponding pixels in the current and previous frame. The similarity between two census vectors within the search area is then computed by measuring the hamming distance. Macro blocks are generated based on the measured hamming distance values and the best match is determined by locating the block that has the smallest sum. The synthesis tool reported that the proposed system is capable of processing 400 standard VGA frames per second.