DocumentCode
2492296
Title
Programmable Switch for Shared Bus Replacement
Author
Ahonen, Tapani ; Nurmi, Jari
Author_Institution
Inst. of Digital & Comput. Syst., Tampere Univ. of Technol.
fYear
0
fDate
0-0 0
Firstpage
241
Lastpage
244
Abstract
A switching interconnection architecture with programmable priorities is described. The switch has been designed to replace shared buses in order to increase bandwidth in the local clusters of large systems-on-chip. The design features guaranteed service for the highest priority input port and best effort service for the rest. Suitable standard cell switch fabrics are discussed and their implementations compared. A memory space conserving programming model for the switch is presented together with a low latency arbiter design
Keywords
asynchronous circuits; integrated circuit design; logic design; programmable circuits; system buses; system-on-chip; low latency arbiter; memory space conserving programming model; programmable switch; shared bus replacement; standard cell switch fabrics; switching interconnection architecture; systems-on-chip; Bandwidth; Communication switching; Delay; Fabrics; Global communication; Network-on-a-chip; Proposals; Routing; Switches; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Research in Microelectronics and Electronics 2006, Ph. D.
Conference_Location
Otranto
Print_ISBN
1-4244-0157-7
Type
conf
DOI
10.1109/RME.2006.1689941
Filename
1689941
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