• DocumentCode
    2493040
  • Title

    A Hybrid Flash Memory SSD Scheme for Enterprise Database Applications

  • Author

    Nam, Byung-Woo ; Na, Gap-Joo ; Lee, Sang-Won

  • Author_Institution
    Sch. of Inf. & Commun. Engr., Sungkyunkwan Univ., Suwon, South Korea
  • fYear
    2010
  • fDate
    6-8 April 2010
  • Firstpage
    39
  • Lastpage
    44
  • Abstract
    Flash memory has many advantages such as high performance, low electronic power, non-volatile storage and physical stability, over hard-disks. For this reason, flash memory has been deployed as data storage for mobile devices, including PDAs, MP3 players, laptop-computers and database systems. According to the cell type, flash memory can be divided into SLC(Single Level Chip) and MLC(Multi Level Chip). In general, SLC is known to have high performance and longer lifetime (i.e. more than 100 K wear-leveling) while MLC is to offer larger capacity and with low price but have wear leveling of not longer than 10 K. In this paper, we show that it is possible to design a fast and cost-efficient storage by combining two types of flash memories in a hybrid fashion. Specifically, we propose a hybrid flash memory solid state disk(SSD) scheme using FAST FTL for enterprise applications, where SLC chip is used as the log space for FAST while MLC chips store the normal data blocks. SLC chips allow fast and durable performance for write while MLC chips provide the large capacity. And, this is mainly due to the FAST FTL algorithm´s characteristics: it tends to direct the random writes to SLC chips and direct the other most random read to MLC chips. By taking the advantages of both chip types, we can find an economically desirable flash SSD design option. Experimental results show that our hybrid flash SSD scheme outperforms MLC-only flash scheme by far both in terms of performance and price.
  • Keywords
    business data processing; database management systems; flash memories; data storage; enterprise database applications; flash memory solid state disk; flash translation layer; hybrid flash memory SSD scheme; multilevel chip; nonvolatile storage; physical stability; single level chip; wear leveling; Database systems; Delay; File systems; Flash memory; Nonvolatile memory; Personal digital assistants; Power generation economics; Production facilities; Solid state circuits; Stability; Database; FTL; Hybrid Flash Memory; NAND Flash Memory; OLTP;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Web Conference (APWEB), 2010 12th International Asia-Pacific
  • Conference_Location
    Busan
  • Print_ISBN
    978-1-7695-4012-2
  • Electronic_ISBN
    978-1-4244-6600-9
  • Type

    conf

  • DOI
    10.1109/APWeb.2010.70
  • Filename
    5474157