• DocumentCode
    2496140
  • Title

    Enhanced power supply structure with new mesh wiring and electroless plated shunt line and assembly-stress-relaxation structure

  • Author

    Nishio, Taichi ; Ishikawa, Kazuhiro ; Itoh, Fumito ; Itoh, Yutaka ; Karatani, Chikako ; Koike, Koji ; Ota, Yukitoshi ; Takahashi, Masao ; Hirano, Hiroshige

  • Author_Institution
    Panasonic Corp., Kyoto
  • fYear
    2008
  • fDate
    1-2 Dec. 2008
  • Firstpage
    65
  • Lastpage
    68
  • Abstract
    In a recent LSI, IR drop on power supply lines is a significant problem for high speed operation, along with an increase of power consumption. In addition, relaxing external stresses during assembly processes is also a serious issue, because more fragile low-k materials are applied to interlayer dielectric films. In this paper, we have developed new structures without adding global interconnect layers. Against the IR drop issue, we have developed 2 different structures. The first structure is the new mesh wiring structure and we have successfully reduced IR drop by 20%. The second structure is the electroless plated shunt line structure and we have successfully obtained reduction in resistance of power supply lines by 38%. To the issue of relaxing stresses, we have succeeded in reducing an assembly stress to 7% with electroless plating. These results indicate that superior structure of global layers can be realized without an increase in chip cost.
  • Keywords
    assembling; electric resistance; electroplating; large scale integration; power consumption; power supply circuits; stress relaxation; wiring; LSI; assembly-stress-relaxation structure; electroless plated shunt line structure; high speed operation; interconnect layers; interlayer dielectric films; low-k materials; mesh wiring structure; power consumption; power supply lines; Assembly; Costs; Dielectric films; Dielectric materials; Energy consumption; Large scale integration; Power supplies; Shape; Stress; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Packaging Workshop of Japan, 2008. VPWJ 2008. IEEE 9th
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-1-4244-3498-5
  • Type

    conf

  • DOI
    10.1109/VPWJ.2008.4762209
  • Filename
    4762209