DocumentCode
2496192
Title
An efficient procedure for obtaining implication relations and its application to redundancy identification
Author
Ichiahra, Hideyuki ; Kajihara, Seiji ; Kinoshita, Kozo
Author_Institution
Dept. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Fukuoka, Japan
fYear
1998
fDate
2-4 Dec 1998
Firstpage
58
Lastpage
63
Abstract
The procedure used in static learning extracts implication relations of the logic circuit. The number of extracted implication relations depends on the order of signal lines processed. In this paper we propose an efficient method to extract implication relations by considering the order of signal lines to be processed. Experimental results show that the proposed order finds more implication relations than others and is effective for redundancy identification
Keywords
VLSI; circuit optimisation; integrated circuit design; logic CAD; redundancy; VLSI; implication relations; logic CAD; logic circuit; redundancy identification; signal lines; static learning; Application software; Boolean functions; Circuit testing; Computer science; Data structures; Fires; Logic circuits; Logic functions; Physics; Signal processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 1998. ATS '98. Proceedings. Seventh Asian
ISSN
1081-7735
Print_ISBN
0-8186-8277-9
Type
conf
DOI
10.1109/ATS.1998.741586
Filename
741586
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