A BIST structure to test delay faults in a scan environment

When stuck-at faults are targeted, scan design reduces the complexity of the test problem. But for delay fault testing, the standard scan structures are not so efficient, because delay fault testing requires the application of dedicated consecutive two-pattern tests. In a standard scan environment, pre-determined two pattern tests cannot be applied to the circuit under test because of the serial shifting procedure. In the literature, different scan modification possibilities have been proposed for applying delay fault oriented deterministic test patterns. Another issue of the delay fault testing problem in scan-based sequential circuits is presented in this paper. The solution combines a BIST structure with the standard scan design