DocumentCode
2499096
Title
A scalable FPGA architecture for non-linear SVM training
Author
Papadonikolakis, Markos ; Bouganis, Christos-Savvas
Author_Institution
Dept. of Electr. & Electron. Eng., Imperial Coll. London, London
fYear
2008
fDate
8-10 Dec. 2008
Firstpage
337
Lastpage
340
Abstract
Support vector machines (SVMs) is a popular supervised learning method, providing state-of-the-art accuracy in various classification tasks. However, SVM training is a time-consuming task for large-scale problems. This paper proposes a scalable FPGA architecture which targets a geometric approach to SVM training based on Gilbertpsilas algorithm using kernel functions. The architecture is partitioned into floating-point and fixed-point domains in order to efficiently exploit the FPGApsilas available resources for the acceleration of the non-linear SVM training. Implementation results present a speed-up factor up to three orders of magnitude of the most computational expensive part of the algorithm compared to the algorithmpsilas software implementation.
Keywords
field programmable gate arrays; learning (artificial intelligence); support vector machines; Gilbert algorithm; fixed-point domain; floating-point domain; kernel functions; nonlinear SVM training; scalable FPGA architecture; supervised learning method; support vector machines; Acceleration; Computer architecture; Field programmable gate arrays; Kernel; Large-scale systems; Partitioning algorithms; Software algorithms; Supervised learning; Support vector machine classification; Support vector machines;
fLanguage
English
Publisher
ieee
Conference_Titel
ICECE Technology, 2008. FPT 2008. International Conference on
Conference_Location
Taipei
Print_ISBN
978-1-4244-3783-2
Electronic_ISBN
978-1-4244-2796-3
Type
conf
DOI
10.1109/FPT.2008.4762412
Filename
4762412
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