A two-stage amplifier with active miller compensation

Author

Tan, Min ; Zhou, Qianneng

Author_Institution

Analog Integrated Circuit Design Dept., CETC, Chongqing, China

fYear

2011

fDate

24-26 June 2011

Firstpage

201

Lastpage

204

Abstract

A two-stage amplifier with active miller compensation is presented in this paper. Unlike the two-stage amplifier with conventional miller compensation, the proposed structure doesn´t contain right half plane zero. What is more, a left half plane zero is created to cancel the first non-dominant pole. The proposed structure improves the bandwidth significantly and reduces the dimension of the compensation capacitor. The proposed two-stage amplifier is designed and simulated in standard 0.6 μm CMOS process. Simulation results show that the unit-gain frequency is increased by 9.4 times with only 38% increase in power consumption. The overall FoM is improved by 31.5 times.

Keywords

CMOS analogue integrated circuits; amplifiers; capacitors; compensation; CMOS process; active Miller compensation; compensation capacitor; left half plane zero; nondominant pole cancellation; power consumption; size 0.6 mum; two-stage amplifier; unit-gain frequency; Analog integrated circuits; Bandwidth; Capacitors; Equivalent circuits; Frequency response; Poles and zeros; Transconductance; bandwidth; miller capacitor; miller compensation; pole-zero; stability; two-stage amplifier;

fLanguage

English

Publisher

ieee

Conference_Titel

Anti-Counterfeiting, Security and Identification (ASID), 2011 IEEE International Conference on

Conference_Location

Xiamen

ISSN

Pending

Print_ISBN

978-1-61284-631-6

Type

conf

DOI

10.1109/ASID.2011.5967452

Filename

5967452