DocumentCode
2502518
Title
On the parametric failures of SRAM in a 3D-die stack considering tier-to-tier supply cross-talk
Author
Yueh, Wen ; Chatterjee, Subho ; Trivedi, Amit ; Mukhopadhyay, Saibal
Author_Institution
Sch. of ECE, Georgia Inst. of Technol., Atlanta, GA, USA
fYear
2012
fDate
23-25 April 2012
Firstpage
264
Lastpage
269
Abstract
This paper analyzes the supply crosstalk between logic cores and SRAMs on separate tiers in a 3D die-stack using a distributed RLC based 3D power grid model. The analysis shows that due to the supply cross-talk power variation in cores modulates the performances and parametric failures in SRAM.
Keywords
SRAM chips; crosstalk; failure analysis; integrated circuit reliability; logic circuits; 3D power grid model; 3D-die stack; SRAM; crosstalk power variation; distributed RLC; logic cores; parametric failures; tier-to-tier supply crosstalk; Impedance; Noise; Pins; Power system stability; Random access memory; Stability analysis; Through-silicon vias; 3D integration; Power Delivery Network; parametric failure; static random access memory (SRAM);
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium (VTS), 2012 IEEE 30th
Conference_Location
Hyatt Maui, HI
ISSN
1093-0167
Print_ISBN
978-1-4673-1073-4
Type
conf
DOI
10.1109/VTS.2012.6231064
Filename
6231064
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