Power Characterization of Embedded SRAMs for Power Binning

While IC speed binning is commonplace today, power binning is a relatively new practice and doing that on an automatic test equipment (ATE), without the aid of functional patterns, is even more rare. As with speed binning, power binning depends on measuring power of multiple components in each IC and using the measurements in a model to predict actual power dissipation of the chip. Power dissipated by embedded SRAMs, especially under activity levels found in normal operation, is critical to power binning. This paper describes a method for measuring the normal functional power of embedded SRAMs by re-using memory BIST and JTAG circuitry in an ATE environment, contributing to power binning at wafer probe.