A generalized hardware implementation of MIMO fading channels

Author

Zhan, Zhan ; Jun, Jiang ; Ping, Zhang ; Xin, Wang

Author_Institution

Key Lab. of Universal Wireless Commun., Beijing Univ. of Posts & Telecommun., Beijing, China

fYear

2009

fDate

28-30 Sept. 2009

Firstpage

594

Lastpage

597

Abstract

Based on field programmable gate array (FPGA) and general computer platform, a generalized emulator of spatiotemporally correlated multiple/input multiple/output (MIMO) channel is realized. In detail, a 2times2 MIMO channel emulator, including 24 clusters delay and 20 sub-paths delay per cluster, using 41% of on-chip block memories, 97% of dedicated multipliers, and 53% of configurable slices of Xilinx Virtex-5 XC5VLX330T-2 FPGA, is proposed. Verification of the proposed MIMO channel fading emulator is accomplished by the realization of dynamic spatial channel model (SCM) and Kronecker model. The hardware platform provides powerful tools for performance simulation of the MIMO wireless links, testing of the wireless communication equipment and evaluation of base-band algorithms.

Keywords

MIMO communication; correlation methods; fading channels; field programmable gate arrays; spatiotemporal phenomena; FPGA; Kronecker model; MIMO fading channel emulator; field programmable gate array; multiple input multiple output system; on-chip block memory; spatial channel model; spatiotemporal correlated channel; wireless communication equipment; Communication industry; Delay; Electronic mail; Electronics industry; Fading; Field programmable gate arrays; Hardware; MIMO; Scattering; Wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications and Information Technology, 2009. ISCIT 2009. 9th International Symposium on

Conference_Location

Icheon

Print_ISBN

978-1-4244-4521-9

Electronic_ISBN

978-1-4244-4522-6

Type

conf

DOI

10.1109/ISCIT.2009.5341178

Filename

5341178