Package and chip design optimization for mid-frequency power distribution decoupling

Author

Garben, Bernd ; Katopis, George A. ; Becke, Wiren D.

Author_Institution

IBM Lab., Boeblingen, Germany

fYear

2002

fDate

21-23 Oct. 2002

Firstpage

245

Lastpage

248

Abstract

In this paper the mid-frequency power supply noise has been studied for a complex, next generation computer system by simulations of the complete module and board power distribution system. An MCM-D and MCM-C design and the effectiveness of on-chip and discrete on-module decoupling capacitors have been compared. The impact of delta-I ramping over several cycles and the impact of the continuous background switching and on-chip leakage have been analyzed. Conclusions are presented to optimize the chip and package design.

Keywords

capacitors; circuit noise; digital circuits; integrated circuit design; integrated circuit noise; leakage currents; multichip modules; power supply circuits; switching; MCM-C design; MCM-D design; board power distribution system; chip design optimization; continuous background switching; delta-I ramping; discrete on-module decoupling capacitors; mid-frequency power distribution decoupling; mid-frequency power supply noise; multi-chip module; next generation computer system; on-chip decoupling capacitors; on-chip leakage; package design optimization; Capacitance; Capacitors; Chip scale packaging; Clocks; Design optimization; Electronic mail; Frequency; Laboratories; Power distribution; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Performance of Electronic Packaging, 2002 IEEE 11th Topical Meeting on

Conference_Location

Monterey, CA, USA

Print_ISBN

0-7803-7451-7

Type

conf

DOI

10.1109/EPEP.2002.1057924

Filename

1057924