Modeling and estimation of leakage in sub-90 nm devices

CMOS technology has witnessed aggressive scaling over the last couple of decades. This has resulted in better performance, higher integration density and increased on-chip functionality. The threshold voltage has been aggressively scaled down, oxides have been drastically thinned and the MOS transistor channels have been suitable engineered to meet the high performance criteria. However, all these have resulted in an increase in transistor leakage and have posed serious bottlenecks to further ´scale´ these super-scaled devices. This paper explores the various dominant leakage mechanisms in scaled devices and examines their trends with scaling. Leakage estimation in circuits has also been presented.