Synthesis of low power high performance dual-VT PTL circuits

Although major portion of power dissipation in present generation CMOS circuits (250 nm-180 nm) is due to charging and discharging of various node capacitors, known as switching power, the leakage power is becoming more and more predominant in ultra-deep submicron (UDSM) technologies. In pass-transistor logic (PTL) circuits, the output of each PTL cell is provided with a buffer to reduce delay and restore voltage level. These buffers, in turn, are the primary source of leakage power in PTL circuits. In this paper we have proposed, for the first time, the use of transistors of two threshold voltages (dual-V_T) to minimize leakage power. We have extended our existing algorithm for logic synthesis of dual-V_T PTL circuits. The extended algorithm has been tested for a large number of ISCAS benchmark circuits. Experimental results show that the use of dual-V_T leads to a reduction in leakage power of about 45% in active mode and 76% in standby mode compared to their single-V_T realization. Moreover, total power dissipation reduces by 18% with respect to single-V_T realizations.