• DocumentCode
    2509538
  • Title

    Object-oriented approach to rapid custom instruction design

  • Author

    Kallel, Emna ; Aoudni, Yassine ; Abid, Mohamed

  • Author_Institution
    CES Lab., Univ. Sfax, Sfax, Tunisia
  • fYear
    2012
  • fDate
    6-8 June 2012
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Due to continuous evolution of Systems-on-Chip (SoC), the complexity of their design and development has augmented exponentially. To deal with the ever-growing complexity of such embedded systems, we introduce, in this paper, an object-oriented approach to rapid SoC design using auto-generation of hardware custom instructions to simplify and accelerate the SoC design process. In our approach, a Data Flow Graph (DFG) is adopted as a representation of the arithmetic operation to convert it to a custom instruction. Then VHDL code will be automatically generated. The input C code is automatically updated for calling the new hardware components. To prove the effectiveness of the proposed approach, a Java source code framework named Automatic Custom Architecture generator (ACAgen) is developed. Experimental results on 3D sample application validate our approach and demonstrate how the proposed framework facilitates and accelerates the SoC design process at low costs.
  • Keywords
    Java; circuit complexity; data flow graphs; electronic engineering computing; embedded systems; hardware description languages; integrated circuit design; object-oriented programming; program compilers; system-on-chip; 3D sample application; ACAgen; C code; DFG; Java source code framework; SoC design process; VHDL code; arithmetic operation; auto-generation; automatic custom architecture generator; continuous evolution; data flow graph; embedded systems; hardware components; hardware custom instructions; object-oriented approach; rapid SoC design; rapid custom instruction design; systems-on-chip; Embedded systems; Field programmable gate arrays; Generators; Hardware; Java; Program processors; System-on-a-chip; ACAgen; DFG; SoC design; automatic VHDL code generation; custom instruction;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Faible Tension Faible Consommation (FTFC), 2012 IEEE
  • Conference_Location
    Paris
  • Print_ISBN
    978-1-4673-0822-9
  • Type

    conf

  • DOI
    10.1109/FTFC.2012.6231733
  • Filename
    6231733