A novel 2.5bit SHA-less MDAC design for 10bit 100Ms pipeline ADC

A sub circuit block - 2.5bit MDAC used in 10 bit 100MHz pipeline ADC fabricated in TSMC 0.35um process is presented in this paper. The pipeline ADC removes a front Sample and Hold block (SH) to save power dissipation and area. However, the aperture error between the multiplying digital-to-analog converter (MDAC) and the comparators in the sub flash may increases in large amount. It obviously decreases the precision of sample phase. In this paper, there are two ways to decrease the aperture error. Furthermore, in order to improve the accuracy of sample signal, a simplified boost-strapped switch is adopted in first 2.5bit SHA-less MDAC design, which only uses one capacitor to restore the adding voltage. The result shows that the MDAC consume 30.73 mW under 3.3v power supply. The settling time is 3ns for input signal at Nyquist rate of 50mHz.