Reset careabouts in a SoC design

Advances in VLSI technology have enabled designers to integrate more functionality in one chip. One of the major design complexities arising from this is defining the reset architecture for a SoC, especially when there are multiple clock domains. Incorrect assumptions or overlooked issues might cause silicon bugs requiring costly re-spins or even worse to a missed opportunity. In this paper, various careabouts that help achieve first pass silicon success as well as reduced verification and manufacturing test generation effort with respect to the reset signal and the reset state are described.