System structure template based transaction level modeling

In the field of SoC hardware/software co-design and electric system level design, architecture modeling is the basis of SoC high level mapping. This paper considers a novel transaction level modeling approach for various SoC architectures and design purpose. A system structure template based transaction level modeling approach is proposed to support template-level design reuse. The approach builds some typical system structure templates such as system function template (SFT) and architecture template (AT), which can customize architectures according to specific application purpose. Experiments results from JPEG encoder applications show that the SST approach can improve the quality and efficiency of SoC design greatly.