A graph rewriting approach to replace asynchronous RAMs in circuits with cycles for FPGAs

Circuit design that minimizes the number of clock cycles is easy if we use asynchronous read operations. However, most of FPGAs support synchronous read operations, but do not support asynchronous read operations. It is one of the main difficulties for users to implement parallel and hardware algorithms in FPGAs. The main contribution of this paper is to provide one of the potent approaches to resolve this problem. We assume that a circuit which includes cycles using asynchronous RAMs designed by a non-expert or quickly designed by an expert is given. Our goal is to convert this circuit with asynchronous RAMs into an equivalent synchronous ones. The resulting circuit with synchronous RAMs can be embedded into the FPGAs.