Advanced silicon IC interconnect technology: present trends and RF wireless implications

Back-end-of-the-line (BEOL) trends in silicon ICs include fully planarized interconnect structures with six levels on non-local wiring, copper metallization for improved resistance and electromigration and low dielectric constant (low-k) interlevel dielectrics (ILDs) for reduced line and coupling capacitance. These technological advances, when combined with front-end silicon technology innovations, will impact technology trends in RF wireless ICs and enhance the potential for systems-on-a-chip and application specific ICs (ASICs) with embedded communications capability. Design complexity will be alleviated by use of intellectual property (IP) cores and virtual design environment (VDE) software. Si IC BEOL trends are summarized, synergistic front-end developments discussed, implications for wireless technologies presented, the impacts of a VDE with IP cores discussed, and a timetable for practical realization in wireless products projected