DocumentCode
2516763
Title
Effectiveness of using supply voltage as back-gate bias in ground plane SOI MOSFET
Author
Kim, Chris H. ; Ananthan, Hari ; Jae-Joon Kim ; Roy, Kaushik
Author_Institution
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
fYear
2004
fDate
4-7 Oct. 2004
Firstpage
69
Lastpage
70
Abstract
We show that GP-SOI MOSFETs are optimal for the DBB scheme offering high on-current and low design complexity without having power performance issues related to the forward-biased p-n junction current in bulk CMOS. It is also shown that GP-SOI can deliver the same performance as DG-SOI 90X lower standby leakage by dynamically switching the back-gate bias.
Keywords
MOSFET; elemental semiconductors; leakage currents; p-n junctions; semiconductor device models; silicon-on-insulator; Si; back gate bias switching; bulk CMOS technology; digital body biasing method; dynamical switching; forward-biased p-n junction current; ground plane SOI MOSFET; leakage currents; CMOS technology; Computer hacking; Insulation; Inverters; Land surface temperature; MOSFET circuits; P-n junctions; Power dissipation; Temperature sensors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 2004. Proceedings. 2004 IEEE International
Conference_Location
Charleston, SC, USA
Print_ISBN
0-7803-8497-0
Type
conf
DOI
10.1109/SOI.2004.1391559
Filename
1391559
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