DocumentCode
2516849
Title
0.6 mu m high speed BiCMOS technology with emitter-base self-aligned structure
Author
Yoshimura, T. ; Yamada, S. ; Yamauchi, T. ; Shimauchi, Y. ; Inayoshi, K.
Author_Institution
Fujitsu Ltd., Kawasaki, Japan
fYear
1989
fDate
3-6 Dec. 1989
Firstpage
241
Lastpage
244
Abstract
A high-speed BiCMOS technology called emitter-base self-aligned BiCMOS (ESBiC) has been developed. This process combines the polysilicon emitter-base self-aligned bipolar transistor with a 0.6- mu m-gate CMOS transistor. With this process, a 15-GHz cutoff frequency and an ECL (emitter-coupled logic) basic delay time of 60 ps at I/sub cs/=1 mA are achieved. For the BiCMOS gate, a 200-ps basic delay and a 330-ps delay time with 0.5-pF load capacitance are obtained.<>
Keywords
BIMOS integrated circuits; bipolar transistors; integrated circuit technology; integrated logic circuits; 0.5 pF; 0.6 micron; 1 mA; 15 GHz; 60 to 330 ps; ECL; ESBiC; cutoff frequency; delay time; emitter-base self-aligned structure; high speed BiCMOS technology; load capacitance; polysilicon emitter-base self-aligned bipolar transistor; propagation delay time; BiCMOS integrated circuits; Bipolar transistors; Boron; Cutoff frequency; Delay; Electrodes; Fabrication; MOS devices; MOSFETs; Resistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1989. IEDM '89. Technical Digest., International
Conference_Location
Washington, DC, USA
ISSN
0163-1918
Print_ISBN
0-7803-0817-4
Type
conf
DOI
10.1109/IEDM.1989.74270
Filename
74270
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