DocumentCode
2516989
Title
Parallel semiconductor device simulation: from power to ´atomistic´ devices
Author
Asenov, A. ; Brown, A.R. ; Roy, S.
Author_Institution
Dept. of Electron. & Electr. Eng., Glasgow Univ., UK
fYear
1998
fDate
19-21 Oct. 1998
Firstpage
58
Lastpage
61
Abstract
This paper discusses various aspects of the parallel simulation of semiconductor devices on mesh connected MIMD platforms with distributed memory and a message passing programming paradigm. We describe the spatial domain decomposition approach adopted in the simulation of various devices, the generation of structured topologically rectangular 2D and 3D finite element grids and the optimisation of their partitioning using simulated annealing techniques. The development of efficient and scalable parallel solvers is a central issue of parallel simulations and the design of parallel SOR, conjugate gradient and multigrid solvers is discussed. The domain decomposition approach is illustrated in examples ranging from ´atomistic´ simulation of decanano MOSFETs to simulation of power IGBTs rated for 1000 V.
Keywords
MOSFET; circuit simulation; conjugate gradient methods; differential equations; distributed memory systems; finite element analysis; insulated gate bipolar transistors; message passing; parallel algorithms; power bipolar transistors; semiconductor device models; simulated annealing; 1000 V; 2D finite element grids; 3D finite element grids; atomistic devices; atomistic simulation; conjugate gradient solvers; decanano MOSFETs; distributed memory; domain decomposition approach; mesh connected MIMD platforms; message passing programming paradigm; multigrid solvers; optimisation; parallel SOR; parallel semiconductor device simulation; parallel simulation; partitioning; power IGBTs; power devices; semiconductor devices; simulated annealing techniques; spatial domain decomposition approach; structured topologically rectangular finite element grids; Computational modeling; Computer architecture; Electronic mail; Finite element methods; Insulated gate bipolar transistors; Mesh generation; Message passing; Parallel programming; Semiconductor devices; Simulated annealing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computational Electronics, 1998. IWCE-6. Extended Abstracts of 1998 Sixth International Workshop on
Conference_Location
Osaka, Japan
Print_ISBN
0-7803-4369-7
Type
conf
DOI
10.1109/IWCE.1998.742707
Filename
742707
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