Low temperature silicon circuit layering for three-dimensional integration

We report a thin device layer (∼1 μm) transfer technique that allows wafer scale transplanting of fully fabricated circuits of SOI on to a host substrate to produce 3-D integrated circuits. This 3-D Parallel Layering Process (3-D PLP) uses temperature below 330 C and incorporates BCB as the dielectric bonding layer. The technique is particularly suitable for 3-D mixed-signal or heterogeneous integration applications where digital and RF/analog circuits benefit from separate manufacturing. Device layer to layer alignment of 3 μm is demonstrated. Electrical measurement of the transistors on the SOI donor wafer before and after transfer process is presented.