10 GHz low phase noise fully integrated VCOs in 130 nm high resistivity CMOS/SOI for 40 Gbits/s datacom

Author

Axelrad, D. ; De Foucauld, E. ; Vincent, P. ; Belleville, M. ; Gaffiot, F.

Author_Institution

CEA-LETI, Grenoble, France

fYear

2004

fDate

4-7 Oct. 2004

Firstpage

174

Lastpage

176

Abstract

This paper discusses the 10 GHz low phase noise fully integrated VCOs in 130 nm high resistivity CMOS/SOI for 40 Gbits/s datacom. This work is a first step towards the evaluation of SOI technology for 40 Gbit/s applications. In particular, CMOS/SOI technologies allow the design of high speed, high performance VCOs and key blocks for high data rate designs. Useful advantages over bulk processes (especially with high resistivity SOI substrates) include high-Q passives, as well as better substrate insulation. Several architectures for a differential VCO, destined to be part of a four phase LC ring VCO, were designed in order to analyze the influence of passives and filtering techniques on phase noise.

Keywords

CMOS integrated circuits; elemental semiconductors; integrated circuit design; phase noise; semiconductor device noise; silicon-on-insulator; voltage-controlled oscillators; 10 GHz; 130 nm; 40 Gbit/s; CMOS circuits; SOI technology; Si; complementary metal-oxide-semiconductor; datacom devices; differential VCO; filtering techniques; four phase LC ring VCO; high resistivity CMOS/SOI; low phase noise fully integrated VCO; passives; silicon-on-insulator; substrate insulation; voltage controlled oscillator; CMOS technology; Conductivity; Filters; Inductors; Parasitic capacitance; Phase noise; Q factor; Tuning; Varactors; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2004. Proceedings. 2004 IEEE International

Print_ISBN

0-7803-8497-0

Type

conf

DOI

10.1109/SOI.2004.1391604

Filename

1391604