• DocumentCode
    2518355
  • Title

    Temporary Bonding of Wafer to Carrier for 3D-Wafer Level Packaging

  • Author

    Shuangwu, Mark Huang ; Pang, David Li Wai ; Nathapong, Suthiwongsunthom ; Marimuthu, Pandi

  • Author_Institution
    Tech. Div., STATS CHIPPAC Ltd., Nanyang, Singapore
  • fYear
    2008
  • fDate
    9-12 Dec. 2008
  • Firstpage
    405
  • Lastpage
    411
  • Abstract
    With great demand of high-end applications such as high-integration microelectronics, system-in-packaging (SiP), power application and flexible ICs, a device wafer needs to be thinned down and further structured, for example, fabrication of through-silicon via for the improved performance. Therefore, handling of ultrathin wafer (less than 100¿m in thickness) becomes a great challenge for both front-end and back-end processes. In current practice, a supportive carrier substrate inclusive of silicon, ceramic, glass and tape is used to protect the thinned device wafer from cracking and deforming and make front-end, assembly and test easier to process. The materials used for bonding the device wafer onto the above mentioned substrates play a critical role in the fabrication of ultrathin devices and high-performance packages. This paper covers two parts: temporary bonding of a device wafer onto a carrier wafer and debonding after completion of the entire through-silicon-via (TSV) process. The purpose of temporary bonding is to attach the device wafer onto the rigid carrier substrate prior to the back-grinding and subsequent processes and thus prevent cracking and chipping of thinned device wafer. The temporary bonding agent allows the release of the device wafer using different approaches such as heat, UV and solvent, etc. The bonding defects such as delamination, bubbling, thickness variation and chemical attack are discussed. Much endeavor is put onto the temporary bonding materials and process optimization. Two types of temporary bonding adhesives are studied to bond a device wafer onto a glass wafer.
  • Keywords
    bubbles; delamination; silicon; system-in-package; wafer bonding; wafer level packaging; 3D-wafer level packaging; Si; SiO2; back-end process; bubbling; ceramic substrate; delamination; device wafer; front-end process; glass substrate; high-integration microelectronics; silicon substrate; system-in-packaging; temporary bonding; through-silicon via process; ultrathin wafer; Assembly; Ceramics; Fabrication; Glass; Microelectronics; Packaging; Protection; Silicon; Testing; Wafer bonding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Packaging Technology Conference, 2008. EPTC 2008. 10th
  • Conference_Location
    Singapore
  • Print_ISBN
    978-1-4244-2117-6
  • Electronic_ISBN
    978-1-4244-2118-3
  • Type

    conf

  • DOI
    10.1109/EPTC.2008.4763468
  • Filename
    4763468