An asynchronous finite impulse response filter design for Digital Signal Processing circuit

Author

Liang Men ; Jia Di

Author_Institution

Dept. of Comput. Sci. & Comput. Eng., Univ. of Arkansas, Fayetteville, AR, USA

fYear

2014

fDate

3-6 Aug. 2014

Firstpage

25

Lastpage

28

Abstract

The clockless feature of asynchronous circuit promotes its application in Digital Signal Processing (DSP) under special applications such as ultra-low power and extreme environments. In this paper, Finite Impulse Response (FIR) filter is implemented in delay-insensitivity asynchronous circuit using the pipeline architecture of Multi-Threshold NULL Conventional Logic (MTNCL). The computing units with different pipeline stages and pattern delay shift registers are integrated as 4 designs of FIR filter using the IBM 130nm 8RF process. Simulation results demonstrate the tradeoff between system throughput and energy efficiency, as the number of pipeline stage changes in the circuit.

Keywords

FIR filters; asynchronous circuits; delay circuits; digital signal processing chips; shift registers; DSP; FIR filter; IBM 8RF process; MTNCL; asynchronous finite impulse response filter design; delay-insensitivity asynchronous circuit; digital signal processing circuit; energy efficiency; extreme environments; multithreshold NULL conventional logic; pattern delay shift registers; pipeline architecture; pipeline stage changes; pipeline stages; size 130 nm; system throughput; ultra-low power; Adders; Computer architecture; Finite impulse response filters; Logic gates; Pipelines; Shift registers; Finite Impulse Response filter; asynchronous circuit; energy efficiency; pipelined architecture; system throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on

Conference_Location

College Station, TX

ISSN

1548-3746

Print_ISBN

978-1-4799-4134-6

Type

conf

DOI

10.1109/MWSCAS.2014.6908343

Filename

6908343