A subthreshold SRAM cell tolerant to random dopant fluctuations

In this paper, we propose a subthreshold SRAM cell tolerant to random dopant fluctuations. The proposed 12T structure has a lower power consumption and larger write and read SNMs. In addition, the read operation is performed differentially at a high read current. The improvements are obtained at the cost of additional area. In addition, the proposed cell adds one junction capacitance per cell to the bitlines. Using SOI/FINFET structures the added capacitance may be minimized. To evaluate the efficiency of the proposed cell structure, several parameters of SRAM and their variations under random dopant fluctuations are studied. In the study, different subthreshold SRAM structures are implemented and compared using a 32nm standard bulk MOSFET technology.