Delay variation analysis in the presence of power supply noise in nano-scale digital VLSI circuits

Author

Bozorgzadeh, Bardia ; Shahdoost, Shahab ; Afzali-Kusha, Ali

Author_Institution

Electr. Eng. & Comput. Sci. Dept., Case Western Reserve Univ., Cleveland, OH, USA

fYear

2014

fDate

3-6 Aug. 2014

Firstpage

117

Lastpage

120

Abstract

In this paper, a novel analytical model is proposed to predict the delay variation due to the power supply noise in nanotechnologies. First, an analytical model is derived for the special case of an inverter gate; next, it is shown that the derived model can also be applied to the other gates. The proposed analytical model helps us to better understand the main contributors to the delay variation and provides an accurate prediction of the delay variation due to the power supply noise in nano-scale VLSI circuits. The accuracy of the proposed model is verified with SPICE simulation in 90nm and 45nm predictive technology models. The maximum error of the proposed model is 7.5% and 8.3% in 90nm and 45nm technologies respectively.

Keywords

VLSI; delays; integrated circuit modelling; integrated circuit noise; integrated logic circuits; logic gates; nanoelectronics; power supply circuits; SPICE simulation; analytical model; delay variation analysis; inverter gate; nanoscale digital VLSI circuits; nanotechnology; power supply noise; predictive technology models; size 45 nm; size 90 nm; Delays; Integrated circuit modeling; Inverters; Logic gates; Noise; Power supplies; Predictive models; Delay variation; Digital VLSI circuits; Power supply noise; Signal integrity; Timing Analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2014 IEEE 57th International Midwest Symposium on

Conference_Location

College Station, TX

ISSN

1548-3746

Print_ISBN

978-1-4799-4134-6

Type

conf

DOI

10.1109/MWSCAS.2014.6908366

Filename

6908366