• DocumentCode
    2520242
  • Title

    Advanced Analysis of WLCSP Copper Interconnect Reliability under Board Level Drop Test

  • Author

    Tee, Tong Yan ; Tan, Long Bin ; Anderson, Rex ; Ng, Hun Shen ; Low, Jim Hee ; Khoo, Choong Peng ; Moody, Robert ; Rogers, Boyd

  • fYear
    2008
  • fDate
    9-12 Dec. 2008
  • Firstpage
    1086
  • Lastpage
    1095
  • Abstract
    The Wafer Level Chip Scale Package (WLCSP) is gaining popularity for its performance and for its ability to meet miniaturization requirements of portable consumer electronics, such as cell phones. Due to differential bending between the silicon die and the PCB and the large stiffness difference, board level drop/bend tests are widely accepted methods to evaluate damage in the parts when a handheld device is dropped by the consumer. Through an aggressive product development program which includes experiment and simulation Amkor has developed the next level of WLCSP (CSPnlTM), a product which exhibits superior board level reliability when subjected to drop impact, a strong requirement for portable electronics. The common industrial qualification criterion is for the product to withstand at least 40 drops before first failure (FF) under the JEDEC drop test condition of 1500 G/0.5 ms. With optimal CSPnl and PCB designs, recent test results show that a typical Amkor CSPnl with a die size of 5.4 mm × 5.4 mm has a minimum failure-free life of over 1000 drops. For an enhanced CSPnl design, first-failure life of 4860 drops. was recorded in actual drop testing. These excellent results imply that much larger die are possible for future CSPnl products, opening the door for wider applications of WLCSP devices, e.g. in next-generation portable electronics with greater function integration.
  • Keywords
    chip scale packaging; integrated circuit interconnections; printed circuit testing; printed circuits; reliability; wafer level packaging; PCB; board level drop test; failure modes; interconnect reliability; spring effect; stress trap; stress-strength ratio; wafer level chip scale package; Cellular phones; Chip scale packaging; Consumer electronics; Copper; Electronics packaging; Handheld computers; Life testing; Product development; Silicon; Wafer scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics Packaging Technology Conference, 2008. EPTC 2008. 10th
  • Conference_Location
    Singapore
  • Print_ISBN
    978-1-4244-2117-6
  • Electronic_ISBN
    978-1-4244-2118-3
  • Type

    conf

  • DOI
    10.1109/EPTC.2008.4763574
  • Filename
    4763574