Flipping-based high speed VLSI architecture for 2-D lifting DWT

In this paper, a flipping-based high speed VLSI architecture for lifting-based 2-D DWT is proposed. The direct implementation of lifting equation has long critical path delay. To reduce the critical path, the flipping structure is widely used. In the proposed architecture, the multipliers in flipping structure are replaced by shift-and-add algorithm. This reduces the critical path delay to one adder (T_α), which is the minimum possible delay any DWT architecture can have. Thus, the proposed architecture is suitable for high-speed applications and has 100% hardware utilization with low control complexity. The architecture is described using VHDL and implemented on FPGA.