Ground plane SOI MOSFET based SRAM with consideration of process variation

Author

Saremi, Mehdi ; Ebrahimi, Behzad ; Afzali-Kusha, Ali

Author_Institution

Nanoelectron. Center of Excellence, Univ. of Tehran, Tehran, Iran

fYear

2010

fDate

15-17 Dec. 2010

Firstpage

1

Lastpage

4

Abstract

In this paper, the characteristics of static random access memory (SRAM) cells based on three silicon-on-insulator (SOI) device structures are studied using device simulations. The comparative study, which is performed in a 32nm standard CMOS technology, includes read static noise margin (read SNM), read current, and standby power. The structures include SOI with ground plane in substrate (SOI-GPS), SOI with ground plane in buried oxide (SOI-GPB), and SOI without ground plane (SOI-WGP). In addition, the variations of the SRAM characteristics due to channel length and thin-film thickness variations are investigated. The results show that the SOI-GPS structure is more resistant against the process variations when compared to the other two structures.

Keywords

CMOS digital integrated circuits; MOSFET; SRAM chips; silicon-on-insulator; SRAM; channel length; device simulations; ground plane SOI MOSFET; ground plane in buried oxide; process variation; read current; read static noise margin; silicon-on-insulator device structures; size 32 nm; standard CMOS technology; standby power; static random access memory cells; thin-film thickness variations; CMOS integrated circuits; Logic gates; MOSFET circuits; Nanoscale devices; Noise; Random access memory; Threshold voltage; Silicon-on-insulator (SOI) MOSFET; ground plane (GP); process variations; static random access memory (SRAM) cell;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2010 IEEE International Conference of

Conference_Location

Hong Kong

Print_ISBN

978-1-4244-9997-7

Type

conf

DOI

10.1109/EDSSC.2010.5713733

Filename

5713733