A single-PLL UWB frequency synthesizer using current reusing SSB mixer

Author

Li, Wei ; Cheng, K.K.M.

Author_Institution

EE Dept., Chinese Univ. of Hongkong, Hong Kong, China

fYear

2010

fDate

15-17 Dec. 2010

Firstpage

1

Lastpage

4

Abstract

This paper presents a fast switching frequency synthesizer for a Mode-1 MB-OFDM UWB system. The proposed architecture with a new frequency plan is designed to simplify the synthesizer implementation for optimizing the system power consumption and sideband rejection ratio. This frequency generator consists of a single phase-lock-loop (PLL), a 12-phase coupled ring oscillator, tri-mode divider-by-2 circuit and a current reused single sideband mixer (SSB). The circuit is fabricated in a 0.18-μm CMOS process and it consumes 18.7mA from a 1.2V power supply. It achieves a switching time of about 3nS, and the unwanted sideband rejection ration of less than 31dBc, and the phase noise of about -103dBc/Hz@1MHz.

Keywords

CMOS integrated circuits; OFDM modulation; frequency synthesizers; mixers (circuits); multiplexing; phase locked loops; ultra wideband technology; 12-phase coupled ring oscillator; CMOS; Mode-1 MB-OFDM UWB system; current 18.7 mA; current reused single sideband mixer; current reusing SSB mixer; fast switching frequency synthesizer; frequency generator; sideband rejection ratio; single phase-lock-loop; single-PLL UWB frequency synthesizer; size 0.18 mum; system power consumption; tri-mode divider-by-2 circuit; voltage 1.2 V; CMOS integrated circuits; Frequency synthesizers; Mixers; OFDM; Switches; Switching circuits; Frequency Synthesizer; Phase-lock-loop(PLL); ultra-wideband(UWB);

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2010 IEEE International Conference of

Conference_Location

Hong Kong

Print_ISBN

978-1-4244-9997-7

Type

conf

DOI

10.1109/EDSSC.2010.5713753

Filename

5713753