Fast locking PLL with all-digital locked-aid circuit

Author

Hsieh, Fu-Jen ; Kao, Shao-Ku

Author_Institution

Chang Gung Univ., Taoyuan, Taiwan

fYear

2010

fDate

15-17 Dec. 2010

Firstpage

1

Lastpage

4

Abstract

A fast locking PLL with all-digital locked-aid circuit is proposed and analyzed. The proposed topology is based on two tuning loops: a frequency detector and a phase detector. A frequency detector is used for accelerate frequency locking time, and a phase detector is used to adjust fine phase error between reference and feedback clock. The proposed PLL circuit is designed based on the 0.35um CMOS process with 3.3V supply voltage. Experiment result shows that the locking time of the proposed PLL can be reduced over 87.5% in comparison with PLL that without locked-aid circuit.

Keywords

CMOS digital integrated circuits; circuit feedback; circuit tuning; clocks; digital phase locked loops; phase detectors; CMOS process; all-digital locked-aid circuit; fast locking PLL circuit; feedback clock; fine phase error adjustment; frequency detector; frequency locking; phase detector; size 0.35 mum; tuning loop; voltage 3.3 V; Clocks; Detectors; Voltage-controlled oscillators; PLL; dual slop; fast acquisition; fast lock; locked-aid;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits (EDSSC), 2010 IEEE International Conference of

Conference_Location

Hong Kong

Print_ISBN

978-1-4244-9997-7

Type

conf

DOI

10.1109/EDSSC.2010.5713762

Filename

5713762