An integrated circuit for the in situ characterization of CMOS best-process micromachining

Author

Warneke, Brett ; Pister, Kristofer S J

Author_Institution

Berkeley Sensor & Actuator Center, California Univ., Berkeley, CA, USA

fYear

2000

fDate

2000

Firstpage

333

Lastpage

338

Abstract

We have developed an integrated circuit for in situ monitoring and characterization of CMOS post-process micromachining. In our demonstration, the circuit provides automated readout of N-well resistors surrounding each of 140 micromachining test structures at up to 14,000 samples per second per device during the post-process silicon etch. We use this circuit to examine the effect of pit size, surrounding thin film layers, and topography in a 2 μm CMOS process with a XeF ₂ post-process step, although the circuit and results are of use to EDP, TMAH, and plasma post-processing

Keywords

CMOS integrated circuits; etching; integrated circuit design; micromachining; process monitoring; CMOS post-process micromachining; EDP post-processing; N-well resistors; TMAH post-processing; automated readout; in situ characterization; in situ monitoring; integrated circuit development; micromachining test structures; on-chip circuit design; pit design; pit size effect; plasma post-processing; post-process silicon etch; surrounding thin film layers; topography effect; Automatic testing; CMOS integrated circuits; Circuit testing; Etching; Micromachining; Monitoring; Resistors; Silicon; Surfaces; Thin film circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design, 2000. Proceedings. 13th Symposium on

Conference_Location

Manaus

Print_ISBN

0-7695-0843-X

Type

conf

DOI

10.1109/SBCCI.2000.876051

Filename

876051