• DocumentCode
    2523858
  • Title

    An Efficient Algorithm for Communication-Based Task Mapping

  • Author

    Cruz, Eduardo H. M. ; Diener, Matthias ; Pilla, Laercio L. ; Navaux, Philippe O. A.

  • Author_Institution
    Inf. Inst., Fed. Univ. of Rio Grande do Sul, Porto Alegre, Brazil
  • fYear
    2015
  • fDate
    4-6 March 2015
  • Firstpage
    207
  • Lastpage
    214
  • Abstract
    The communication between tasks of a parallel application is an important characteristic to consider when mapping tasks to computing cores due to possible differences in communication performance. Within a machine, performance differences are introduced by the memory hierarchy, in which cache memories can be shared by groups of cores and intra-chip interconnections are faster than inter-chip interconnections. In cluster and grid systems, the network imposes an additional communication latency. By mapping tasks that communicate to cores nearby on the memory hierarchy, or to the same nodes in clusters or grids, the communication of parallel applications is optimized, leading to increased performance and energy efficiency. In the task mapping context, one of the most important aspects to be considered is the mapping algorithm, as it determines the improvements that can be achieved. Since the problem of finding the best mapping is NP-Hard, heuristics must be employed to find an approximate solution in feasible time. In this paper, we present Eager Map, a new algorithm to perform communication-based mapping that is based on a greedy grouping strategy applied hierarchically. Experimental evaluation indicates that the execution time of our algorithm is 10 times faster than the state-of-the-art, and presents higher performance improvements. Due to its low execution time and high stability, Eager Map is also suitable for online task mapping, where tasks are migrated during execution.
  • Keywords
    approximation theory; cache storage; computational complexity; parallel architectures; Eager Map; NP-hard problem; cache memories; communication-based task mapping; greedy grouping strategy; intra-chip interconnections; memory hierarchy; online task mapping; parallel architectures; Algorithm design and analysis; Cache memory; Complexity theory; Computer architecture; Hardware; Program processors; Topology; communication; hardware topology; memory hierarchy; task mapping;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel, Distributed and Network-Based Processing (PDP), 2015 23rd Euromicro International Conference on
  • Conference_Location
    Turku
  • ISSN
    1066-6192
  • Type

    conf

  • DOI
    10.1109/PDP.2015.25
  • Filename
    7092722