A distributed BIST technique for diagnosis of MCM interconnections

Author

Pendurkar, Rajesh ; Chatterjee, Abhijit ; Zorian, Yervant

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

fYear

1998

fDate

18-23 Oct 1998

Firstpage

214

Lastpage

221

Abstract

A general description of an enhanced scheme for designing completely self-testable MCMs is given. It allows performance testing and diagnosis of MCM interconnections for dynamic effects. This scheme is based on embedding of cascadable test pattern generators and reconfigurable signature analyzers into the design of MCM dies. A theory of partitioning of linear registers is applied to devise a two phase distributed diagnosis strategy The design of a novel MISR reconfiguration scheme that enables high diagnosis resolution, is presented. Simulation results obtained confirm the effectiveness of our BIST technique

Keywords

automatic testing; built-in self test; design for testability; digital simulation; integrated circuit interconnections; logic partitioning; logic testing; multichip modules; shift registers; MCM interconnections; MISR reconfiguration; cascadable test pattern generators; distributed BIST; distributed diagnosis; dynamic effects; embedding; fault diagnosis; linear registers; partitioning; performance testing; reconfigurable signature analyzers; self-testable MCM; simulation; two phase distributed diagnosis; Assembly; Automatic testing; Built-in self-test; Costs; Delay effects; Fault detection; Fault diagnosis; Packaging; Pattern analysis; Propagation delay;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1998. Proceedings., International

Conference_Location

Washington, DC

ISSN

1089-3539

Print_ISBN

0-7803-5093-6

Type

conf

DOI

10.1109/TEST.1998.743154

Filename

743154