A thread and data-parallel MPEG-4 video encoder for a system-on-chip multiprocessor

Author

Jacobs, Tom R. ; Chouliaras, Vassilios A. ; Nunez-Yanez, Jose L.

Author_Institution

Dept. of Electron. & Electr. Eng., Univ. of Loughborough, UK

fYear

2005

fDate

23-25 July 2005

Firstpage

405

Lastpage

410

Abstract

We studied the dynamic instruction count reduction for a single-thread, vectorized and a multithreaded, nonvectorized, MPEG-4 video encoder. Results indicate a maximum improvement of the order of 88% for 22 CPU contexts for the multithreaded case whereas the single-thread, vectorized version demonstrates an 85% improvement for a vector register file length of 24 bytes, over the scalar case. We present VLSI macrocells of a vector accelerator implementing a subset of the MPEG-4 vector ISA and a 2-way, parametric, bus-based, cache coherent, SoC multiprocessor.

Keywords

VLSI; digital signal processing chips; system-on-chip; video coding; MPEG-4 video encoder; VLSI macrocell; dynamic instruction count reduction; multithreaded video encoder; single-thread video encoder; system-on-chip multiprocessor; vector accelerator; vectorized video encoder; Discrete cosine transforms; Embedded computing; MPEG 4 Standard; Macrocell networks; Parallel processing; System-on-a-chip; Transform coding; Very large scale integration; Video compression; Yarn;

fLanguage

English

Publisher

ieee

Conference_Titel

Application-Specific Systems, Architecture Processors, 2005. ASAP 2005. 16th IEEE International Conference on

ISSN

2160-0511

Print_ISBN

0-7695-2407-9

Type

conf

DOI

10.1109/ASAP.2005.11

Filename

1540416