Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS

Author

Hiienkari, M. ; Teittinen, J. ; Koskinen, L. ; Turnquist, M. ; Kaltiokallio, M. ; Makipaa, J. ; Rantala, A. ; Sopanen, M.

Author_Institution

Technol. Res. Center, Univ. of Turku, Turku, Finland

fYear

2014

fDate

6-9 Oct. 2014

Firstpage

1

Lastpage

2

Abstract

To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This paper presents an ASIC implementation of a 32-bit RISC CPU in 28nm CMOS with wide range of adjustable voltage/frequency from 250mV/85kHz to 750mV/135MHz. The CPU employs timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing energy efficiency at a given operating point. Measurements show 3.15pJ/cyc energy consumption at 400mV, which corresponds to 39% energy savings and 83% EDP improvement compared to operation based on static signoff timing.

Keywords

CMOS digital integrated circuits; application specific integrated circuits; clocks; reduced instruction set computing; ASIC implementation; clock stretching; digital circuit; energy consumption minimization; frequency 85 kHz to 135 MHz; near-threshold voltage; size 28 nm; static signoff timing; subthreshold voltage; timing-error prevention; ultra-wide voltage range RISC CPU; voltage 250 mV to 750 mV; word length 32 bit; Central Processing Unit; Clocks; Energy consumption; Energy measurement; Latches; Timing; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014 IEEE

Conference_Location

Millbrae, CA

Type

conf

DOI

10.1109/S3S.2014.7028192

Filename

7028192