Analog performance of short-channel asymmetric self-cascode of junctionless nanowire nMOS transistors

This work presented an evaluation of self-cascode association of short-channel junctionless nanowire transistors, by means of experimental results, comparing data of this configuration to single transistors. Even though the self-cascode transistors have shown to reduce de drain current and transconductance level with respect to single device, due to their longer effective channel length, this effect becomes pronounced with the widening of the transistor close to the drain (M_D), with consequent threshold voltage reduction. Both symmetric and asymmetric self-cascode configurations do not degrade the efficiency of converting current into transconductance (g_m/I_DS ratio) in relation to single transistor with same length. On the contrary, the increase of width of M_D is capable of reducing the output conductance, reaching values smaller than those obtained for longer single transistors, especially at low gate voltages. The combination of these characteristics results in improved performance for the self-cascode configured as common-source amplifier if compared to symmetric self-cascode or individual longer transistors, reaching a voltage gain increase of up to 17 dB at g_m/I_DS = 15V^-1. When used as common-drain amplifiers, the asymmetric self-cascode junctionless transistors has shown to improve the electrical characteristics (voltage gain and input voltage range) in comparison to a short-channel single transistor, whereas had not shown advantages over a longer single device.