Effect of back gate on parasitic bipolar effect in FD SOI MOSFETs

Author

Fanyu Liu ; Ionica, I. ; Bawedin, M. ; Cristoloveanu, S.

Author_Institution

IMEP-LAHC, MINATEC, Grenoble, France

fYear

2014

fDate

6-9 Oct. 2014

Firstpage

1

Lastpage

2

Abstract

In short-channel fully-depleted (FD) silicon-on-insulator (SOI) MOSFETs, the drain leakage current is enhanced by the parasitic bipolar transistor. The parasitic bipolar effect is induced by band-to-band tunneling and floating-body effects. It strongly depends on film thickness and back-gate voltage. We show experimentally the possibility to reduce the parasitic bipolar effect by biasing the back gate (ground plane). Based on devices simulations, we discuss the origin of the bipolar action, its suppression and the possible applications.

Keywords

MOSFET; bipolar transistors; leakage currents; semiconductor device models; silicon-on-insulator; tunnelling; FD SOI MOSFETs; back-gate voltage; band-to-band tunneling effects; device simulations; drain leakage current; film thickness; floating-body effects; parasitic bipolar effect; parasitic bipolar transistor; short-channel fully-depleted silicon-on-insulator MOSFETs; Bipolar transistors; Junctions; Leakage currents; Logic gates; MOSFET; Silicon-on-insulator; Tunneling; FD SOI; back gate; band-to-band tunneling; parasitic bipolar effect;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014 IEEE

Conference_Location

Millbrae, CA

Type

conf

DOI

10.1109/S3S.2014.7028210

Filename

7028210