Influence of underlap on UTBB SOI MOSFETs in dynamic threshold mode

This paper discusses the influence of extensionless lengths (0nm-self aligned, 15nm and 20nm) on UTBB (Ultra-Thin-Body-and-Buried oxide) SOI (Silicon-On-Insulator) devices operating in conventional (V_B=0V), Dynamic Threshold (DT2, where V_B=V_G) and enhanced Dynamic Threshold (eDT, where V_B=kV_G) modes. The extensionless device of 20nm (underlap between gate and source/drain) presents better SS (Subthreshold Swing), DIBL (Drain Induced Barrier Lowering), GIDL (Gate Induced Drain Leakage), transistor efficiency (gm/I_D), V_EA (Early Voltage) and AV (Intrinsic Voltage Gain). A large improvement was also observed experimentally when these devices operate under DT2 and eDT modes thanks to better coupling between the front and back gates, except for the GIDL that degrades due to a higher tunneling current near the drain caused by the higher transversal electric field.