• DocumentCode
    2525738
  • Title

    FakeFault: a silicon debug software tool for microprocessor embedded memory arrays

  • Author

    Kwon, Young-Jun ; Mathew, Ben ; Hao, Hong

  • Author_Institution
    Silicon Graphics Comput. Syst., Mountain View, CA, USA
  • fYear
    1998
  • fDate
    18-23 Oct 1998
  • Firstpage
    727
  • Lastpage
    732
  • Abstract
    This paper presents a simple but elegant approach to effectively automate the time-consuming silicon debug procedure for microprocessor embedded memory arrays that allow no direct test modes, based on sequential ATPG with built-in design-for-debug methodology
  • Keywords
    automatic test pattern generation; automatic test software; boundary scan testing; built-in self test; computer debugging; design for testability; embedded systems; fault simulation; integrated circuit testing; microprocessor chips; software tools; FakeFault; built-in design-for-debug methodology; internal scan; memory dump procedure; microprocessor embedded memory arrays; scan latches location; scan test vectors; sequential ATPG; silicon debug software tool; structured DFT; Automatic test pattern generation; Automatic testing; Clocks; Data mining; Microprocessors; Observability; Pins; Registers; Silicon; Software tools;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Conference, 1998. Proceedings., International
  • Conference_Location
    Washington, DC
  • ISSN
    1089-3539
  • Print_ISBN
    0-7803-5093-6
  • Type

    conf

  • DOI
    10.1109/TEST.1998.743217
  • Filename
    743217
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2525738