The role of radiation effects in SOI technology development

Author

Palkuti, L. ; Alles, M. ; Hughes, H.

Author_Institution

Defense Threat Reduction Agency, Ft Belvior, VA, USA

fYear

2014

fDate

6-9 Oct. 2014

Firstpage

1

Lastpage

2

Abstract

The technical development of radiation resistant CMOS/SOI technologies is reviewed. Inherent hardness of SOI to dose rate upset and latchup has leveraged major developments of SOI technologies. TID hardness for up to the 150nm node was addressed by process hardening. Inherent hardness of 45nm and 32nm technologies reduced the need for TID hardening. As technology is scaled to 28nm and 14nm nodes TID hardening is again required. SEU hardening is addressed by circuit design for a wide range of technologies with significant SEU improvement for 28nm and 14nm is observed.

Keywords

CMOS integrated circuits; radiation hardening (electronics); silicon-on-insulator; SEU improvement; SOI technology development; TID hardness; dose rate upset; latchup; process hardening; radiation effects; radiation resistant CMOS technologies; silicon-on-insulator electronics; size 14 nm; size 28 nm; technical development; CMOS integrated circuits; CMOS technology; Error analysis; Latches; Radiation hardening (electronics); Resistance; Single event upsets; CMOS/SOI; Radiation resistant; SEE effects; TID effects;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014 IEEE

Conference_Location

Millbrae, CA

Type

conf

DOI

10.1109/S3S.2014.7028233

Filename

7028233