Monolithic IC integration key alignment aspects for high process yield

Lithographic scaling has been the main growth driver to follow Moore´s law of cost reduction and performance increase for several decades. However, the 22nm node appears to be a game changer, where other core processes besides lithography have to be taken into account. Monolithic integration is one solution, where lithographic scaling is replaced by integration in vertical direction. Stacking and electrically contacting several semiconductor layers is challenging, as multiple unit processes have to be solved and put together. One of the key processes for monolithic integration is aligned wafer-to-wafer bonding. Besides optimization of the alignment accuracy, particle cleaning or plasma activation, earlier processing steps have important influence to a high yield processing of monolithic integrated circuits.