On-line software-based self-test of the Address Calculation Unit in RISC processors

Author

Bernardi, P. ; Ciganda, L. ; De Carvalho, M. ; Grosso, M. ; Lagos-Benites, J. ; Sanchez, E. ; Reorda, M. Sonza ; Ballan, O.

Author_Institution

Dipt. di Autom. e Inf., Politec. di Torino, Torino, Italy

fYear

2012

fDate

28-31 May 2012

Firstpage

1

Lastpage

6

Abstract

Software-based Self-Test (SBST) can be used during the mission phase of microprocessor-based systems to periodically assess the hardware integrity. However, several constraints are imposed to this approach, due to the coexistence of test programs with the mission application. This paper proposes a method for the generation of SBST programs to test on-line the Address Calculation Unit of embedded RISC processors, which is one of the most heavily impacted by the online constraints. The proposed strategy achieves high stuck-at fault coverage on both a MIPS-like processor and an industrial 32-bit pipelined processor; these two case studies show the effectiveness of the technique and the low effort.

Keywords

automatic testing; built-in self test; computer architecture; fault diagnosis; logic testing; microprocessor chips; reduced instruction set computing; MIPS-like processor; SBST program; address calculation unit; embedded RISC processor; industrial 32-bit pipelined processor; on-line software-based self-test; stuck-at fault coverage; Adders; Circuit faults; Memory management; Microprocessors; Program processors; Registers; Testing; SBST; SoC; on-line testing; pipelined processors;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium (ETS), 2012 17th IEEE European

Conference_Location

Annecy

Print_ISBN

978-1-4673-0696-6

Electronic_ISBN

978-1-4673-0695-9

Type

conf

DOI

10.1109/ETS.2012.6233004

Filename

6233004