DocumentCode
2528352
Title
Interconnection scheme for improved high speed ICs
Author
Plettner, A. ; Haberger, K. ; Englmaier, A. ; Hartmann, H. ; Neumeier, K.
Author_Institution
Fraunhofer-Inst. for Solid State Technol., Munchen, Germany
fYear
1994
fDate
11-14 Dec. 1994
Firstpage
121
Lastpage
124
Abstract
In this paper, a technology based on the Bonded Etch-back Silicon On Insulator (BESOI) technique is proposed which employs a highly conductive layer buried beneath the insulating oxide layer, and therefore is advantageous for high frequency ICs. No additional mask level is required and the necessary technological steps can be done by the wafer manufacturer. The design freedom is hardly limited.<>
Keywords
buried layers; digital integrated circuits; integrated circuit interconnections; integrated circuit metallisation; silicon-on-insulator; BESOI technique; Si; bonded etch-back SOI technique; buried highly conductive layer; high frequency ICs; high speed ICs; insulating oxide layer; interconnection scheme; CMOS technology; Dielectric losses; Frequency; Implants; Integrated circuit interconnections; Manufacturing; Oxidation; Semiconductor films; Silicon on insulator technology; Wafer bonding;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1994. IEDM '94. Technical Digest., International
Conference_Location
San Francisco, CA, USA
ISSN
0163-1918
Print_ISBN
0-7803-2111-1
Type
conf
DOI
10.1109/IEDM.1994.383449
Filename
383449
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